Low-Latency Adiabatic Quantum-Flux-Parametron Circuit Integrated With a Hybrid Serializer/Deserializer

Adiabatic quantum-flux-parametron (AQFP) logic is an ultra-low-power superconductor family. AQFP gates are powered and clocked by dedicated clocking schemes using ac excitation currents to implement energy-efficient switching process, adiabatic switching. We have proposed a low-latency scheme, delay-line clocking, demonstrated basic gates. In order test more complex circuits, serializer/deserializer (SerDes) should be incorporated into the circuit under test, since number of input/output (I/O) cables limited equipment. Therefore, in present study we propose develop novel SerDes for testing delay-line-clocked circuits combining rapid single-flux-quantum (RSFQ) families, which refer as AQFP/RSFQ hybrid SerDes. The comprises RSFQ shift registers facilitate data storage during serial-to-parallel parallel-to-serial conversion. Furthermore, all component identical current synchronize parts. fabricate demonstrate (8-to-3 encoder, largest ever designed) integrated with at 4.2 K up 4.5 GHz. Our measurement results indicate that enables only few I/O thus powerful tool development very large-scale integration circuits.